1. Field of the Invention
The present invention generally relates to a method for assigning power and signal locations in a three-dimensional wiring maze in order to minimize inductively coupled noise in the signal lines as a result of current changes, i.e. so-called Delta-I noise.
For ease and clarity of explanation, the invention will be described in terms of a method for assigning signal and power pins of an integrated circuit module in order to minimize Delta-I noise. Those skilled in the art will recognize that the method is generally applicable to the assignment of signal and power conductor locations in other applications where it is desirable to minimize Delta-I noise.
2. Description of the Prior Art
Delta-I noise can be a limiting factor in device switching speeds and/or the number of devices that can be switched simultaneously. In addition, it can induce false logic levels in the signal lines. Skilled engineers have developed heuristic criteria for the assignment of signal and power pins and have developed methods for the calculation of Delta-I noise for a given assignment pattern. Delta-I noise can be calculated as a function of conductor spacing, conductor diameter, conductor length, and the voltage level of a conductor relative to the voltage level of adjacent conductors.
Existing procedures for determining pin assignment patterns to limit Delta-I noise rely upon the skill and experience of the engineer and are limited by the relatively small number of Delta-I noise calculations that are practical to evaluate a proposed pattern relative to the number of possible patterns in a relatively large pattern. It will be appreciated that an array may have from five-hundred to two-thousand pins.